| Type of Document |
Master's Thesis |
| Author |
Walters, Allison L.
|
| Author's Email Address |
awal@erols.com |
| URN |
etd-11198-212219 |
| Title |
A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform |
| Degree |
Master of Science |
| Department |
Electrical Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Dr. Peter Athanas |
Committee Chair |
| Dr. Mark Jones |
Committee Member |
| Dr. Nathaniel Davis, IV |
Committee Member |
|
| Keywords |
- reconfigurable computing
- digital signal processing
- FIR filters
|
| Date of Defense |
1998-01-30 |
| Availability |
unrestricted |
Abstract
This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
awalters.PDF |
510.47 Kb |
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00:01:12 |
00:01:03 |
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