Type of Document	Master's Thesis
Author	Dailey, David M
URN	etd-11242009-020247
Title	Integration of VHDL simulation and test verification into a Process Model Graph design environment
Degree	Master of Science
Department	Electrical Engineering
Advisory Committee	Advisor Name Title Armstrong, James R. Committee Chair Cyre, Walling R. Committee Member Gray, Festus Gail Committee Member
Keywords	VHDL (Computer hardware description language)
Date of Defense	1994-06-05
Availability	restricted
Abstract see document
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