Title page for ETD etd-11242009-020306


Type of Document Master's Thesis
Author Edwards, Carleen Marie
URN etd-11242009-020306
Title Representation and simulation of a high level language using VHDL
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Cyre, Walling R. Committee Member
Keenan, Michael A. Committee Member
Keywords
  • Programming languages (Electronic computers)
Date of Defense 1994-12-05
Availability restricted
Abstract

This paper presents an approach for representing and simulating High Level Languages (HLL) using VHDL behavioral models. The graphical representation, a Data Flow Graph (DFG), is used as a base for the VHDL representation and simulation of a High Level Language (C). A package of behavioral models for the functional units for the High Level Language as well as individual entities has been developed using VHDL. An algorithm, Graph2VHDL, accepts a Data Flow Graph representation of a High Level Language and constructs a VHDL modol for that graph. The representation of a High Level Language in VHDL frees users of custom cotnputing platforms from the tedious job of devcloping a hardware Inodel for a desired application. The algorithm also constructs a test file that is used with a pre-existing prograln, Test Bench Generation (TBG), to create a test-bench for the VHDL model of a Data Flow Graph. The test bench that is generated is used to simulate the representation of the High Level Language in the Data Flow Graph format. Experimental results verify the representation of the High Level Language in the Data Flow Graph format and in VHDL is correct.

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