Title page for ETD etd-12082009-135511


Type of Document Dissertation
Author Zheng, Yexin
Author's Email Address yexin@vt.edu
URN etd-12082009-135511
Title Circuit Design Methods with Emerging Nanotechnologies
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Huang, Chao Committee Chair
Cao, Yang Committee Member
Hsiao, Michael S. Committee Member
Schaumont, Patrick Robert Committee Member
Yang, Yaling Committee Member
Keywords
  • design automation
  • ant colony optimization
  • satisfiability
  • equivalence checking
  • defect tolerance
  • logic synthesis
  • nanotechnology
  • circuit design
Date of Defense 2009-12-08
Availability unrestricted
Abstract
As complementary metal-oxide semiconductor (CMOS) technology faces

more and more severe physical barriers down the path of

continuously feature size scaling, innovative nano-scale devices

and other post-CMOS technologies have been developed to enhance

future circuit design and computation. These nanotechnologies

have shown promising potentials to achieve magnitude improvement

in performance and integration density. The substitution of CMOS

transistors with nano-devices is expected to not only continue

along the exponential projection of Moore's Law, but also raise

significant challenges and opportunities, especially in the field

of electronic design automation. The major obstacles that the

designers are experiencing with emerging nanotechnology design

include: i) the existing computer-aided design (CAD) approaches in

the context of conventional CMOS Boolean design cannot be directly

employed in the nanoelectronic design process, because the

intrinsic electrical characteristics of many nano-devices are not

best suited for Boolean implementations but demonstrate strong

capability for implementing non-conventional logic such as

threshold logic and reversible logic; ii) due to the density and

size factors of nano-devices, the defect rate of nanoelectronic

system is much higher than conventional CMOS systems, therefore

existing design paradigms cannot guarantee design quality and lead

to even worse result in high failure ratio. Motivated by the

compelling potentials and design challenges of emerging post-CMOS

technologies, this dissertation work focuses on fundamental design

methodologies to effectively and efficiently achieve high quality

nanoscale design.

A novel programmable logic element (PLE) is first proposed to

explore the versatile functionalities of threshold gates (TGs) and

multi-threshold threshold gates (MTTGs). This PLE structure can

realize all three- or four-variable logic functions through

configuring binary control bits. This is the first single

threshold logic structure that provides complete Boolean logic

implementation. Based on the PLEs, a reconfigurable architecture

is constructed to offer dynamic reconfigurability with little or

no reconfiguration overhead, due to the intrinsic self-latching

property of nanopipelining. Our reconfiguration data generation

algorithm can further reduce the reconfiguration cost.

To fully take advantage of such threshold logic design using

emerging nanotechnologies, we also developed a combinational

equivalence checking (CEC) framework for threshold logic

design. Based on the features of threshold logic gates and

circuits, different techniques of formulating a given threshold

logic in conjunctive normal form (CNF) are introduced to

facilitate efficient SAT-based verification. Evaluated with

mainstream benchmarks, our hybrid algorithm, which takes into

account both input symmetry and input weight order of threshold

gates, can efficiently generate CNF formulas in terms of both SAT

solving time and CNF generating time.

Then the reversible logic synthesis problem is considered as we

focus on efficient synthesis heuristics which can provide high

quality synthesis results within a reasonable computation time. We

have developed a weighted directed graph model for function

representation and complexity measurement. An atomic

transformation is constructed to associate the function complexity

variation with reversible gates. The efficiency of our heuristic

lies in maximally decreasing the function complexity during

synthesis steps as well as the capability to climb out of local

optimums. Thereafter, swarm intelligence, one of the machine

learning techniques is employed in the space searching for

reversible logic synthesis, which achieves further performance

improvement.

To tackle the high defect-rate during the emerging nanotechnology

manufacturing process, we have developed a novel defect-aware

logic mapping framework for nanowire-based PLA architecture via

Boolean satisfiability (SAT). The PLA defects of various types are

formulated as covering and closure constraints. The defect-aware

logic mapping is then solved efficiently by using available SAT

solvers. This approach can generate valid logic mapping with a

defect rate as high as 20%. The proposed method is universally

suitable for various nanoscale PLAs, including AND/OR, NOR/NOR

structures, etc.

In summary, this work provides some initial attempts to address

two major problems confronting future nanoelectronic system

designs: the development of electronic design automation tools and

the reliability issues. However, there are still a lot of

challenging open questions remain in this emerging and promising

area. We hope our work can lay down stepstones on nano-scale circuit

design optimization through exploiting the distinctive

characteristics of emerging nanotechnologies.

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