Title page for ETD etd-12162005-144728


Type of Document Master's Thesis
Author Morford, Casey Justin
Author's Email Address cmorford@vt.edu
URN etd-12162005-144728
Title BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D. Committee Chair
Hsiao, Michael S. Committee Member
Martin, Thomas L. Committee Member
Keywords
  • FPGA
  • Partial Reconfiguration
  • Virtex-II Pro
  • Bitstream Manipulation
  • Bitstream
  • Xilinx
  • Virtex-II
  • Dynamic Module Server
Date of Defense 2005-12-15
Availability unrestricted
Abstract
With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.
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