Title page for ETD etd-121699-202818


Type of Document Master's Thesis
Author Atwell, James W.
Author's Email Address jatwell@vt.edu
URN etd-121699-202818
Title A Multiplexed Memory Port for Run Time Reconfigurable Applications
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Armstrong, James R. Committee Member
Jones, Mark T. Committee Member
Keywords
  • FPGA
  • JHDL
  • memory
  • reconfigurable
  • VHDL
  • RTR
Date of Defense 1999-12-13
Availability unrestricted
Abstract
Configurable computing machines (CCMs) are available as plug in cards for standard workstations. CCMs make it possible to achieve computing feats on workstations that were previously only possible with super computers. However, it is difficult to create applications for CCMs. The development environment is fragmented and complex. Compilers for CCMS are emerging but they are in their infancy and are inefficient.

The difficulties of implementing run time reconfiguration (RTR) on CCMs are addressed in this thesis. Tools and techniques are introduced to simplify the development and synthesis of applications and partitions for RTR applications. A multiplexed memory port (MMP) is presented in JHDL and VHDL that simplifies the memory interface, eases the task of writing applications and creating partitions, and makes applications platform independent. The MMP is incorporated into an existing CCM compiler. It is shown that the MMP can increase the compiler's functionality and efficiency.

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