Title page for ETD etd-12182008-221910


Type of Document Dissertation
Author Lim, Hui Fern Michele
Author's Email Address mhflim@vt.edu
URN etd-12182008-221910
Title Low Temperature Co-fired Ceramics Technology for Power Magnetics Integration
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Lee, Fred C. Committee Co-Chair
van Wyk, Jacobus Daniel Committee Co-Chair
Liu, Yilu Committee Member
Lu, Guo-Quan Committee Member
Suchicital, Carlos T. A. Committee Member
Keywords
  • shielding
  • inductor
  • substrate
  • magnetics
  • Low temperature co-fired ceramics
  • power electronics
  • buck converter
Date of Defense 2008-11-17
Availability unrestricted
Abstract
This dissertation focuses on the development of low-temperature co-fired ceramics (LTCC) technology for power converter magnetics integration. Because magnetic samples must be fabricated with thick conductors for power applications, the conventional LTCC process is modified by cutting trenches in the LTCC tapes where conductive paste is filled to produce thick conductors to adapt to this requirement. Characterization of the ceramic magnetic material is performed, and an empirical model based on the Steinmetz equation is developed to help in the estimation of losses at frequencies between 1 MHz to 4 MHz, operating temperature between 25 °C and 70 °C, DC pre-magnetization from 0 A/m to 1780 A/m, and AC magnetic flux densities between 5 mT to 50 mT. Temperature and DC pre-magnetization dependence on Steinmetz exponents are included in the model to describe the loss behavior.

In the development of the LTCC chip inductor, various geometries are evaluated. Rectangular-shaped conductor geometry is selected due to its potential to obtain a much smaller footprint, as well as the likelihood of having lower losses than almond-shaped conductors with the same cross-sectional area, which are typically a result of screen printing. The selected geometry has varying inductance with varying current, which helps improve converter efficiency at light load. The efficiency at a light-load current of 0.5 A can be improved by 30 %. Parametric variation of inductor geometry is performed to observe its effect on inductance with DC current as well as on converter efficiency. An empirical model is developed to describe the change in inductance with DC current from 0 A to 16 A for LTCC planar inductors fabricated using low-permeability tape with conductor widths between 1 mm to 4 mm, conductor thickness 180 μm to 550 μm, and core thickness 170 μm to 520 μm. An inductor design flow diagram is formulated to help in the design of these inductors.

Configuring the inductor as the substrate carrying the semiconductor and the other electronic components is a next step to freeing the surface area of the bulky component and improving the power density. A conductive shield is introduced between the circuitry and the magnetic substrate to avoid adversely affecting circuit operation by having a magnetic substrate in close proximity to the circuitry. The shield helps reduce parasitic inductances when placed in close proximity to the circuitry. A shield thickness in the range of 50 μm to 100 μm is found to be a good compromise between power loss and parasitic inductance reduction. The shield is effective when its conductivity is above 107 S/m. When a shield is introduced between the inductor substrate and the circuitry, the sample exhibits a lower voltage overshoot (47 % lower) and an overall higher efficiency (7 % higher at 16 A), than an inductor without a shield. A shielded active circuitry placed on top of an inductive substrate performs similarly to a shielded active circuitry placed side-by-side with the inductor. Using a floating shield for the active circuitry yields a slightly better performance than using a grounded shield.

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