Title page for ETD etd-12252008-171529


Type of Document Master's Thesis
Author Sun, Yi
Author's Email Address sunyi@vt.edu
URN etd-12252008-171529
Title Modeling and Design of Digitially Controlled Voltage Regulator Modules
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Lee, Fred C. Committee Chair
Wang, Fei Fred Committee Member
Xu, Ming Committee Member
Keywords
  • Digital Control
  • VRMs
  • DPWM
  • Digital Delay
  • Small Signal Model
  • Adaptive Voltage Position
Date of Defense 2008-12-03
Availability unrestricted
Abstract
It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects.

Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more.

To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycle’s resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results.

Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop.

This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phase’s off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a “fast” controller, the current sampling and DPWM might introduce some delay to the loop.

After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller.

With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification.

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