Type of Document	Master's Thesis
Author	O'Connor, R. Brendan
URN	etd-382215659641571
Title	Dataflow Analysis and Optimization of High Level Language Code for Hardware-Software Co-Design
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Dr. Peter Athanas Committee Chair Dr. A. Lynn Abbott none Dr. Nathaniel J. Davis IV none
Keywords	CCM co-design hardware compilation
Date of Defense	1996-05-07
Availability	unrestricted
Abstract Recent advancements in FPGA technology have provided devices which are not only suited for digital logic prototyping, but also are capable of implementing complex computations. The use of these devices in multi-FPGA Custom Computing Machines (CCMs) has provided the potential to execute large sections of programs entirely in custom hardware which can provide a substantial speedup over execution in a general-purpose sequential processor. Unfortunately, the development tools currently available for CCMs do not allow users to easily configure multi-FPGA platforms. In order to exploit the capabilities of such an architecture, a procedure has been developed to perform a dataflow analysis of programs written in C which is capable of several hardware-specific optimizations. This, together with other software tools developed for this purpose, allows CCMs and their host processors to be targeted from the same high-level specification
Files	Filename       Size       Approximate Download Time (Hours:Minutes:Seconds)     28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access    etd.pdf 586.62 Kb 00:02:42 00:01:23 00:01:13 00:00:36 00:00:03   rboconn.pdf 586.62 Kb 00:02:42 00:01:23 00:01:13 00:00:36 00:00:03

If you have questions or technical problems, please Contact DLA.