Title page for ETD etd-4941511109613150


Type of Document Master's Thesis
Author Musgrove, Mark D.
URN etd-4941511109613150
Title VLSI Implementation of a Run-time Reconfigurable Custom Computing Integrated Circuit
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Tront, Joseph G.
Woerner, Brian D.
Athanas, Peter M. Committee Chair
Keywords
  • VLSI
  • run-time reconfigurable
  • configurable computing
  • data flow
  • FPGA
  • DSP
Date of Defense 1996-11-07
Availability unrestricted
Abstract
The growth of high performance computing to date can largely be attributed to continuing breakthroughs in materials and manufacturing.In order to increase computing capacity beyond these physical bounds, new computing paradigms must be developed that make more efficient use of existing manufacturing technologies. Custom Computing Machines (CCMs) are an emerging class of computers that offer promising possibilities for future high-performance computational needs. With the increasing popularity of the run-time reconfigurable (RTR) concept in the CCM community, questions have arisen as to what computational device should be at the heart of an RTR platform. Currently the preferred device, and really the only practical device, has been the RAM-based Field-Programmable Gate Array (FPGA).

Unfortunately, for applications that require high performance, FPGAs are limited by their narrow data path and small computational density. The Colt integrated circuit has been designed from the start to be the computational processing element in an RTR platform. Colt is an RTR data-flow processor array with a course-grain architecture (16-bit data path). This thesis covers the VLSI implementation and verification of the Colt integrated circuit, including the approach and methods necessary to make a functionally working integrated circuit.

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