| Type of Document |
Master's Thesis |
| Author |
Chandrasekhar, Suresh
|
| Author's Email Address |
suresh@ee.vt.edu |
| URN |
etd-71798-84748 |
| Title |
Partitioning Methods and Algorithms for Configurable Computing Machines |
| Degree |
Master of Science |
| Department |
Electrical Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Jones, Mark T. |
Committee Chair |
| Armstrong, James R. |
Committee Member |
| Ha, Dong Sam |
Committee Member |
|
| Keywords |
- Partitioning
- CCM
- FPGA
- Algorithm
|
| Date of Defense |
1998-08-05 |
| Availability |
unrestricted |
Abstract
This thesis addresses the partitioning problem for configurable computing machines. Specifically, this thesis presents algorithms to partition chain-structured task graphs across configurable computing machines. The algorithms give optimal solutions for throughput and total execution time for these problems under constraints on area, pin count, and power consumption. The algorithms provide flexibility for applying these constraints while remaining polynomial in complexity. Proofs of correctness as well as an analysis of runtime complexity are given. Experiments are performed to illustrate the runtime of these algorithms.
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ISDN (128 Kb) |
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suresh2.pdf |
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suresh_front.pdf |
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suresh_title.pdf |
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