| Type of Document |
Master's Thesis |
| Author |
Swanchara, Steven F.
|
| Author's Email Address |
sswan@vt.edu |
| URN |
etd-81598-221016 |
| Title |
An FPGA-Based Multiuser Receiver Employing Parallel Interference Cancellation
|
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Reed, Jeffrey Hugh |
Committee Chair |
| Athanas, Peter M. |
Committee Member |
| Woerner, Brian D. |
Committee Member |
|
| Keywords |
- FPGA
- CDMA
- Multiuser Receiver
- Interference Cancellation
- Configurable Computing
|
| Date of Defense |
1998-07-22 |
| Availability |
unrestricted |
Abstract
Research efforts have shown that capacity in a DS/CDMA cellular system can be increased through the use of digital signal processing techniques that exploit the nature of the multiple access interference (MAI). By jointly demodulating the users in the system, this interference can be characterized and reduced thus decreasing the overall probability of error in the system. Numerous multiuser structures exist, each with varying degrees of complexity and performance. However, the size and complexity of these structures is large relative to a conventional receiver. This effort demonstrates a practical approach to implementing parallel interference cancellation applied to DBPSK DS/CDMA on an FPGA-based configurable computing platform. The system presented acquires, tracks, cancels, and demodulates four users independently and performs various levels of interference cancellation. The performance gain of the receiver in a four-user environment under various levels of noise and cancellation are presented.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
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THESIS.pdf |
790.89 Kb |
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