Title page for ETD etd-82898-162543


Type of Document Master's Thesis
Author Bhoja, Sudeer
Author's Email Address bsudeer@vt.edu
URN etd-82898-162543
Title Optimization of the Assignment of Printed Circuit Cards to Assembly Lines in Electronics Assembly
Degree Master of Science
Department Industrial and Systems Engineering
Advisory Committee
Advisor Name Title
Ellis, Kimberly P. Committee Chair
Kobza, John E. Committee Member
Sullivan, William Committee Member
Keywords
  • Printed Circuit Card Assembly
  • Line Assignment
  • Process Planning
  • Card Grouping
  • Line Balancing
Date of Defense 1998-09-01
Availability unrestricted
Abstract
The focus of this research is the line assignment problem in printed circuit card assembly systems. The line assignment problem involves the allocation of circuit card types to an appropriate assembly line among a set of assembly lines with the objective of reducing the total assembly time. These circuit cards are to be assembled in a manufacturing facility, capable of simultaneously producing a wide variety of printed circuit cards in different production volumes. A set of component types is required for each printed circuit card. The objective is to assign the circuit cards to the assembly line such that the total assembly time, which includes the setup time as well as the processing time required for all card types in a set, is minimized.

The focus of this research is to develop an algorithmic strategy for addressing this problem in electronics assembly. This problem involves considering several interrelated decision problems such as assigning printed circuit cards to assembly lines, grouping circuit cards into families to reduce the number of setups, and assigning component types to machines to balance workload. The line assignment models are formulated as large scale mixed integer programming problems and are solved using a branch-and-bound algorithm, supplemented by techniques for improving the solution time. The models and solution approaches are demonstrated using industry representative data sets and can serve as useful decision support tools for process planning engineers.

Files
  Filename       Size       Approximate Download Time (Hours:Minutes:Seconds) 
 
 28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access 
  etd.pdf 203.32 Kb 00:00:56 00:00:29 00:00:25 00:00:12 00:00:01

Browse All Available ETDs by ( Author | Department )

dla home
etds imagebase journals news ereserve special collections
virgnia tech home contact dla university libraries

If you have questions or technical problems, please Contact DLA.