Title page for ETD etd-8597-10225


Type of Document Master's Thesis
Author Yang, Tsung-Han
Author's Email Address tyang@vt.edu
URN etd-8597-10225
Title A Stream-Based In-Line Allocatable Multiplier for Configurable Computing
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Armstrong, James R.
Davis, Nathaniel J. IV
Athanas, Peter M. Committee Chair
Keywords
  • Multiplier
  • Computer Arithmetic
  • VLSI
Date of Defense 1997-08-29
Availability unrestricted
Abstract

The growing demand for high-performance computing platforms has pushed the computing community to invent new architectures for processors. Recently, researchers have begun to solve the problem by the implementation of Field-Programming Gate Arrays (FPGAs). FPGAs make it possible to implement different applications on the same hardware. Unfortunately, FPGAs suffer from low bandwidth, density, and throughout. To gain the flexibility of FPGAs and to gain more computational capacity than conventional processors have, Wormhole run-time reconfigurable (RTR) techniques has been developed to address some high performance digital signal processing (DSP) problems.

Multiplication is one of the basic functions used in digital signal processing. Most high-performance DSP systems rely on hardware multiplication to achieve high data throughput. To meet the processing needs of DSP, a multiplier was embedded into a prototype wormhole RTR device called Colt, but because each design has its own speed and size requirements, rarely can a designer take an already existing multiplier module and use it in Colt. Therefore redesigning multipliers is necessary for meeting the system specifications of Colt. This thesis explores the design of the multiplier from architecture level to circuit level.

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