Scholarly
    Communications Project


Document Type:Master's Thesis
Name:Allison L. Walters
Email address:awal@erols.com
URN:1998/00101
Title:A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on a FPGA Base Custom Computing Platform
Degree:Master of Science
Department:Electrical Engineering
Committee Chair: Dr. Peter Athanas
Chair's email:athanas@vt.edu
Committee Members:Dr. Nathaniel Davis, IV
Dr. Mark Jones
Keywords:reconfigurable computing,digital signal processing,FIR filters
Date of defense:January 30, 1998
Availability:Release the entire work immediately worldwide.

Abstract:

This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s.

List of Attached Files

awalters.PDF


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