|Document Type:||Master's Thesis|
|Name:||Aaron George Hawes|
|Title:||The Design of an IVDS World Wide Web Browser Architecture|
|Degree:||Master of Science|
|Department:||Electrical and Computer Engineering|
|Committee Chair:||Dr. Nathaniel J. Davis, IV|
|Committee Members:||Dr. Scott F. Midkiff|
|Willard W. Farley|
|Keywords:||Interactive Video Data Service, World Wide Web, Browser, FPGA|
|Date of defense:||November 20, 1997|
|Availability:||Release the entire work immediately worldwide.|
An IVDS (Interactive Video Data Service) uses an interactive television system to transmit data to and from subscribers' homes. IVDS allows the viewer to interact with content provided on the television using a remote control. A typical IVDS application would be ordering an advertised product or playing along with a quiz show.
The Virginia Tech Center for Wireless Telecommunications (CWT), under a contract with Interactive Return Service, Inc., is developing an IVDS system in which content is provided through the television cable system in the form of audio codes. A special remote control can detected these audio codes and query the user for input. The return path for this system is a wireless channel. The remote control contains a spread spectrum transmitter that transmits packets to a Repeater unit residing within a quarter mile of the user's home.
With the popularity of the World Wide Web soaring, many companies are announcing internet appliances that will bring the content of the web to the user at a fraction of the cost of a standard personal computer. CWT has been contracted to extend the core IVDS system to provide a web browsing capability, allowing the user to browse the web with only the remote control. This thesis outlines the requirements of the IVDS Web Browser System. The different hardware design concepts are documented. The final Browser System specification is presented, as well as a board-level description of the Decoder Unit that is part of this final Browser System. Finally, a detailed description, current status, and simulation results are presented for the FPGA (Field Programmable Gate Array) that serves as the controller for the Decoder Unit.
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