Scholarly
    Communications Project


Document Type:Master's Thesis
Name:Yingchun He
Email address:yche@ee.vt.edu
URN:1998/00816
Title:VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip
Degree:Master of Science
Department:The Bradley Department of Electrical and Computer Engineering
Committee Chair: Dr. Peter M. Athanas
Chair's email:athanas@vt.edu
Committee Members:Dr. William H. Tranter
Dr. Mark Jones
Keywords:VLSI, layout, run-time configurable computing
Date of defense:July 14, 1998
Availability:Release the entire work immediately worldwide.

Abstract:

VLSI Implementation of a Run-time Configurable Computing Integrated Circuit The Stallion Chip He, Yingchun (ABSTRACT) Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.

List of Attached Files

etd.pdf


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