Scholarly Communications Project

Document Type:Master's Thesis
Name:Suresh Chandrasekhar
Email address:suresh@ee.vt.edu
URN:1998/00908
Title:Partitioning Methods and Algorithms for Configurable Computing Machines
Degree:Master of Science
Department:Electrical Engineering
Committee Chair: Dr. Mark T. Jones
Chair's email:mtj@vt.edu
Committee Members:Dr. James R. Armstrong
Dr. Dong S. Ha
Keywords:Partitioning, CCM, FPGA, Algorithm
Date of defense:August 5, 1998
Availability:Release the entire work immediately worldwide.

Abstract:

This thesis addresses the partitioning problem for configurable computing machines. Specifically, this thesis presents algorithms to partition chain-structured task graphs across configurable computing machines. The algorithms give optimal solutions for throughput and total execution time for these problems under constraints on area, pin count, and power consumption. The algorithms provide flexibility for applying these constraints while remaining polynomial in complexity. Proofs of correctness as well as an analysis of runtime complexity are given. Experiments are performed to illustrate the runtime of these algorithms.

List of Attached Files

suresh2.pdf suresh_front.pdf suresh_title.pdf

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